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INTEGRATED CIRCUITS
DATA SHEET
UMA1016xT Frequency synthesizer for radio communication equipment
Product specification Supersedes data of June 1992 File under Integrated Circuits, IC03 1995 Jul 12
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
FEATURES * RF input frequencies to 1 GHz * Fully programmable RF divider * 3-wire serial bus interface * On-chip 3 to 16 MHz crystal oscillator * Mask programmable /2 to /31 reference divider ratio * Up to 1 MHz channel spacing * Crystal frequency buffered output * Dual register architecture for fast Tx/Rx switching in TDD single synthesizer systems * Phase detector compensated for supply and temperature variations * Power-down mode. APPLICATIONS * 900 MHz cordless telephones * Portable battery-powered radio equipment. GENERAL DESCRIPTION
UMA1016xT
The UMA1016xT is a low power synthesizer for radio communications. Manufactured in bipolar technology, it is designed for a 70 to 1000 kHz channel spacing in the 500 to 1000 MHz band. The channel is programmed via a 3-wire serial bus. The internal dual register architecture allows a single synthesizer to be used in TDD systems. Fast switching between transmit and receive frequencies is achieved without the need for bus overhead. It also incorporates a sensitive, low power RF divider and a dead-zone-eliminated 3-state phase comparator. A power-down mode enables the circuit to be idled.
QUICK REFERENCE DATA SYMBOL Supply VCC VDD ICC + IDD IDD(pd) fref RFI Tamb supply voltage supply voltage supply current digital supply current in power-down phase comparator frequency RF input frequency operating ambient temperature Tamb = -10 to +70C Tamb = 0 to +70C 4.5 4.5 - - 70 500 500 -10 - - 12 0.8 250 - - - 5.5 5.5 - - 1000 800 1000 +70 V V mA mA kHz MHz MHz C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ORDERING INFORMATION TYPE NUMBER UMA1016AT(1) UMA1016BT(2) UMA1016xT(3) Notes 1. UMA1016AT has a Reference Division Factor of 27. 2. UMA1016AT has a Reference Division Factor of 16. 3. UMA1016xT is a customized version. 1995 Jul 12 2 PACKAGE NAME SO16 SO16 SO16 PIN POSITION plastic small outline package; 16 leads; body width 3.9 mm plastic small outline package; 16 leads; body width 3.9 mm plastic small outline package; 16 leads; body width 3.9 mm VERSION SOT109-1 SOT109-1 SOT109-1
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
BLOCK DIAGRAM
UMA1016xT
Tx/Rx
handbook, full pagewidth
12
CK DATA
10 9
Ck REGISTER D Q REGISTER
UMA1016XT
INTERFACE
EN
11
Tx LATCH
Tx LATCH
RFI
7
AMPLIFIER
RF DIVIDER
MAIN DIVIDER
HPDN VDD DGND
5 3 BIAS GENERATORS Rx LATCH Rx LATCH
6 BUFFER OSCILLATOR DIVIDER 2 - 31
. .
PHASE DETECTOR 15 V 14 CC AGND
16 CP
4
MGA193 - 1
1 RO1
2 RO2
REFCK
Fig.1 Block diagram.
1995 Jul 12
3
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
PINNING SYMBOL RO1 RO2 VDD REFCK HPDN DGND RFI i.c. DATA CK EN TX/RX i.c. AGND VCC CP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION crystal oscillator input or TCXO input oscillator output to crystal circuit 5 V supply to digital section reference crystal frequency buffered output Hardware Power-Down Not; IC operates when pin is HIGH digital ground 1 GHz RF signal input internally connected programming bus data input programming bus clock input programming bus enable input (active LOW) transmit (HIGH)/receive (LOW) mode select input internally connected analog ground 5 V supply to charge pump circuit charge pump output
handbook, halfpage
UMA1016xT
RO1 1 RO2 VDD REFCK HPDN DGND RFI i.c. 2 3 4 UMA1016XT 5 6 7 8
MGA192 - 1
16 CP 15 VCC 14 AGND 13 i.c. 12 TX/RX 11 EN 10 CK 9 DATA
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION General The UMA1016xT is a low power synthesizer for radio communications in the range 500 to 1000 MHz. It includes an oscillator circuit, reference divider, RF divider, 3-state phase and frequency comparator, charge pump and main control circuit for the transfer of serial data into two internal registers. VDD supplies power to the digital circuits while VCC powers the charge pump. VDD and VCC are nominally 5 V but will operate in the range 4.5 V to 5.5 V. Reduced noise coupling is facilitated by separate digital and analog ground pins which must always be externally connected to the same DC potential to prevent the flow of large currents across the die. The synthesizer is placed in idle mode during power-down but the oscillator and buffer remain operative and may be used as a clock for system timing.
Main divider The main divider is a fully programmable pulse-swallow type. Following a sensitive (50 mV, -13 dBm) input amplifier, the RF signal is applied to a 13-bit divider (MD13 to MD1). The division ratio is provided via the serial bus to two 13-bit latches, corresponding to transmit and receive frequencies. The serial programming register is written to under processor control, independently of divider operation. This removes difficulty if using a low data bus transmission speed. The new ratio is transferred to the appropriate latch when the programming enable signal (EN) returns HIGH. The last register bit (PB0) is used to determine whether the new value is loaded into the transmit (PB0 = 1) or receive (PB0 = 0) frequency latch. To avoid spurious phase changes, the divider incorporates the new ratio only at the end of the on-going reference period. The minimum division ratio is 512. One reference cycle is required to update a new ratio. Internal power-on occurs rapidly.
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4
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
Oscillator External capacitive feedback is applied to the common collector Colpitts oscillator which has high voltage supply rejection and negligible temperature drift. It is designed to function as an input buffer without the need for external components when a TCXO or other clock is used. A separate output buffer, which remains active during power-down (HPDN taken LOW), provides a TTL compatible signal to drive external logic circuits (REFCK). Reference divider The reference divider has a fixed divider ratio set by metal masking between 2 and 31. For example, a 4 MHz crystal connected to the oscillator and a /16 ratio allows a channel spacing of 250 kHz. Other frequencies and ratios are possible. Phase comparator The phase comparator combines a phase and frequency detector and charge pump (see Fig.3). The charge pump current is internally fixed and determined for fast switching. It is compensated against power supply and temperature variation. The detector is assembled from dual D-type flip-flops which, together with feedback, remove the `dead' zone. Upon the detection of a phase error, either UP or DO go HIGH. This gates the appropriate current generator to source or sink 1.75 mA at the output pin. When no phase error is detected, CP becomes 3-state. The tuning voltage of the VCO is established from the sum of the current pulses into the loop filter. A simple passive loop filter may be used to offer high performance without requiring an operational-amp. The phase comparator function is summarized in Table 2. Main control interface The programming control interface permits access to two internal latches, denoted Tx and Rx. The serial input bits on DATA, entered MSB first, are converted to a parallel word and stored in the appropriate latch under the control of the last entered register bit (PB0). When this is set
UMA1016xT
HIGH, data serially fed to the register is loaded into the transmit (Tx) latch; when PB0 is LOW, the data is transferred to the receive latch (Rx). The data sent to the synthesizer is loaded in bursts framed by the signal EN. Programming clock edges, together with their appropriate data bits, are ignored until EN becomes active (LOW). The internal latches are updated with the latest programming data when EN returns inactive (HIGH). Only the last 15 bits serially clocked into the device are retained within the programming register. One extra shift register bit (PB7) can be internally added via metal masking to allow direct software compatibility with a 7-bit swallow counter and a 64/65 dual-modulus prescaler. No check is made on the number of clock pulses received during the time that programming is enabled. EN going HIGH while CLOCK is still LOW generates an active clock edge causing a shift of the data bits. Data programmed into the register is lost during power-down (HPDN taken LOW). The maximum serial bus clock speed is specified as 5 MHz. Minimum speed is limited by the clock edge rise and fall times to ensure that no data transparency condition can exist. Independent of any serial programming activity, the RF divider chain uses the data previously stored within the selected latch to determine the synthesized channel frequency. The Tx/Rx signal controls which latch is read to preload the counter bits at each division cycle. When new data is updated into the device, it is used during the cycle following latch selection by the Tx/Rx control line. If the Tx/Rx line is tied LOW, only data loaded into the Rx latch is used. In this event the serial data stream clocked into the synthesizer must terminate with an `0'. The logic diagram for the first bits of the programming interface is shown in Fig.3. The other bits are processed in a similar manner by a further 9 stages of the shift register-latches-multiplexer. The signals supplied to the circuit are described by the timing diagram. The table of values has been specified for maximum bus speed. Under slow clocking conditions, rise and fall times must not be excessively slow.
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Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
Table 1 Main divider division ratio MAIN COUNTER MD1 LSB Table 2 Operation of phase comparator SYMBOL UP DO Ipcd Table 3 FIRST pb14 md13 Note 1. pb7; see Section "Main control interface". pb13 pb12 pb11 md12 md11 md10 Fref < Fvar 0 1 -1.75 mA Fref > Fvar 1 0 +1.75 mA MD2 ../.. MD7 MD8 ../..
UMA1016xT
MD12
MD13 MSB
Fref = Fvar 0 0 <5 nA
Register and latch bit allocations REGISTER AND LATCH BIT ALLOCATIONS pb10 md9 pb9 md8 pb8 md7 pb7(1) X pb6 md6 pb5 md5 pb4 md4 pb3 md3 pb2 md2 pb1 md1 LAST IN pb0 address
VCC
handbook, full pagewidth
var
UP PHASE AND FREQUENCY DETECTOR
on/off
1.75 mA
pump output on/off 1.75 mA
ref
DO
AGND
MGA194
Fig.3 Phase comparator block diagram.
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Fig.4 Simplified interface logic diagram.
handbook, full pagewidth
1995 Jul 12
DATA D
Philips Semiconductors
Frequency synthesizer for radio communication equipment
programming shift register
Q D Q D Q D Q D Q DATA out FLIPFLOP CK FLIPFLOP CK FLIPFLOP CK FLIPFLOP CK FLIPFLOP CK Shift CK
CK PB0
D
Q
D
Q
D
Q
D
Q LATCH
transmit frequency latch
LATCH EN
LATCH EN
LATCH EN
EN Tx Ld
EN
D
Q
FLIPFLOP CK D Q D Q D Q D Q
receive frequency latch
7
LATCH EN End_Count_CK Rx Ld LATCH EN LATCH EN LATCH EN Not_End_Count MUX R OUT SEL Tx / Rx D Q
MGA195
MUX R OUT B SEL B
MUX R OUT SEL B
MUX R OUT SEL B
coefficient select multiplexer
Select
LATCH EN Bit 0 Bit 1 Bit 2 Bit 3
main divider coefficient
UMA1016xT
Product specification
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
UMA1016xT
handbook, full pagewidth
t su
t h1
t cyc
tf
tr
t end
t new
CK
DATA
msb
lsb
ladrs
next
EN t start t wid
MGA196
Fig.5 Logic interface signals.
1995 Jul 12
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Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VCC Vi Tstg Tamb HANDLING PARAMETER digital supply voltage range analog supply voltage range input voltage range storage temperature range operating ambient temperature to ground CONDITIONS MIN. -0.2 -0.2 0 -55 -10
UMA1016xT
TYP. - - - - -
MAX. UNIT 7 7 VDD 125 70 V V V C C
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. TIMING CHARACTERISTICS VDD and VCC = 5 V; Tamb = -10 to +70 C; unless otherwise specified; typical values measured at VCC and VDD = 5 V; Tamb = 25 C; note 1. SYMBOL Serial programming clock (pin 10) fck tr tf Tcy tstart tend twidth tnew tsu th1 Note 1. Minimum and maximum values are for maximum clock speed. clock frequency rise time fall time clock period 200 0.01 - 4 5 5 - - - - - - - 5 50 50 - - - - - - - MHz ns ns ns PARAMETER MIN. TYP. MAX. UNIT
Enable programming (pin 11) delay to rising clock edge delay from last clock edge minimum inactive pulse width delay from EN inactive to new data 30 0 200 300 ns ns ns ns
Register serial input data (pin 9) input data to CK set-up time input data to CK hold time 10 10 ns ns
1995 Jul 12
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Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
CHARACTERISTICS VDD and VCC = 5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Power supply VDD VCC IDD ICC IDD(pd) fvco Vrf(rms) RiRF CiRF N digital voltage supply analog voltage supply digital supply current analog supply current digital supply current in power-down mode Tamb = -10 to +70C Tamb = 0 to +70C input signal voltage level (RMS value) input resistance input capacitance main divider division ratio RF = 1 GHz indicative; not tested VCC = 5.5 V; pump off VCC = VDD 4.5 4.5 VDD = 5.5 V; REFCK off - - - 5 5 10.1 1.9 0.8 - - - 350 1.5 - - - 5 2 5 PARAMETER CONDITIONS MIN.
UMA1016xT
TYP.
MAX.
UNIT
5.5 5.5 10.8 2.1 1.5
V V mA mA mA
RF divider input (RFI) RF frequency range 500 500 50 - - 512 800 1000 200 - - 8191 MHz MHz mV pF
Oscillator and reference divider (RO1, RO2) fref Vosc(rms) Co1 Zo2 Co2 fcp Icp(source) Icp(sink) Icp(leak) Vcp oscillator frequency range sinusoidal input level at pin 1 (RMS value) parasitic capacitance at pin 1 output impedance at pin 2 output capacitance indicative; not tested indicative; not tested indicative; not tested Rref(ck) used 3 0.1 - - - 16 0.5 - - - MHz V pF k pF
Phase comparator and charge pump output (CP) phase detector frequency range charge pump source current charge pump sink current charge pump off leakage current charge pump voltage compliance range Icp within specified range VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V 70 -2.2 1.3 -10 0.5 250 1.75 - - 1000 2.2 +10 kHz mA mA nA -1.75 -1.3
VCC - 0.5 V
1995 Jul 12
10
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
SYMBOL PARAMETER CONDITIONS MIN.
UMA1016xT
TYP. - - - - - 3
MAX.
UNIT
Interface logic input signal levels (HPDN, EN, DATA, CK, Tx/Rx) VIH VIL(PD) VIL Ibias Ci Voh Vol Io(sink) tr tf HIGH level input voltage LOW level input voltage LOW level input voltage input bias current input capacitance all inputs HPDN except HPDN logic 1 logic 0 indicative; not tested Oscillator buffered logic output signal (REFCK) HIGH level driven output voltage LOW level driven output voltage output sink current reference clock output rise time reference clock output fall time VCL = 0.5 V CI = 25 pF CL = 25 pF VDD = 5 V 3.5 0 -0.4 - - 4.0 - - 50 50 VDD - 0.5 V 0.4 - - - V mA ns ns 3 -0.3 -0.3 - -5 - VDD + 0.3 V 0.6 1 5 - - V V A A pF
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11
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
APPLICATION INFORMATION In a typical single-synthesizer application, the circuit is connected as shown in Fig.6. Both analog and digital supplies are decoupled to ground with HF and LF filter capacitors. Correct oscillator operation requires capacitors both to ground and to provide feedback across the amplifier. Five signals are shown fed from a microcontroller to provide serial programming, control TDD frequency selection and initiate the power-down mode. Other system logic may also be clocked by a crystal frequency output from the synthesizer.
UMA1016xT
A passive 2nd-order loop filter giving a 3rd-order system response is shown in Fig.6. Indicated values are intended for rapid frequency switching (500 s), 200 kHz channel spacing (reference /27) and breakthrough levels below -60 dB. The VCO output shows a power splitter supplying both the synthesizer RF input and drive buffer for other system components (RF amplifier in transmit mode, input mixer in receive mode). The minimizing of loop filter node leakage currents requires careful board layout.
handbook, full pagewidth
VP 220 pF 68 pF 33 pF 5.4 MHz 33
1 VP 2 3 REFCK 47 F 4 10 nF 5 6 7 1 nF 8
16 15 14 13
10 nF
47 F
UMA1016XT
12 11 10 9 P4 P3 P2 P1
100
P0 82 12 VCO 18 k
RFout
12
330 pF
4.7 nF
MGA197 - 2
Fig.6 Application diagram.
1995 Jul 12
12
Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm
UMA1016xT
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.050 0.041 0.228
0.028 0.004 0.012
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1995 Jul 12
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Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
SOLDERING SO or SSOP Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering SO Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. SSOP
UMA1016xT
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). METHOD (SO OR SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 C.
1995 Jul 12
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Philips Semiconductors
Product specification
Frequency synthesizer for radio communication equipment
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Application information Where application information is given, it is advisory and does not form part of the specification. Limiting values
UMA1016xT
This data sheet contains target or goal specifications for product development This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1995 Jul 12
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Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 (from 10-10-1995: +31-40-2724825) SCD41 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
413061/1500/03/pp16 Document order number: Date of release: 1995 Jul 12 9397 750 00206

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